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| Categories | Flash Memory IC Chip | 
|---|---|
| Brand Name: | Ti | 
| Model Number: | TPS53659RSBR | 
| Price: | |
| Operating Temperature Range: | - 40 C to + 125 C | 
| Packaging: | Reel | 
| Package / Case: | WQFN-40 | 
| Mounting Style: | SMD/SMT | 
| Maximum Operating Temperature: | + 125 C | 
| Minimum Operating Temperature: | - 40 C | 
TPS53659RSBR Power Path Management IC Power Management Specialized - PMIC FET Controller
1 Features
Full VR13 Server Feature Set Including Digital Input Power Monitor
Programmable Loop Compensations
Configurable with Non-Volatile Memory (NVM) for
Low External Component Counts
Individual Phase Current Calibrations and Reports
Dynamic Phase Shedding with Programmable
Current Threshold for Optimizing Efficiency at Light
and Heavy Loads
Fast Phase-Adding for Undershoot Reduction
(USR)
Backward VR12.0 and VR12.5 Compatible
8-Bit DAC with Selectable 5 mV or 10 mV
Resolution and Output Ranges from 0.25 V to
1.52 V or 0.5 V to 2.8125 V for Dual Channels
Driverless Configuration for Efficient High-
Frequency Switching
2 Applications
• VR13 Memory Power of Server and Telecom Applications
• Fully Compatible with TI NextFETTM Power Stage for High-Density Solutions
• Accurate, Adjustable Voltage Positioning
• Frequency Selections with Closed-loop Frequency
Control: 300 kHz to 1 MHz
• Patented AutoBalanceTM Phase Balancing
• Selectable, 16-level Per-Phase Current Limit • PMBusTM System
Interface for Telemetry of
Voltage, Current, Power, Temperature, and Fault
Conditions
• Dynamic Output Voltage Transitions with
Programmable Slew Rates via SVID or PMBus
Interface
• Conversion Voltage Range: 4.5 V to 17 V
• Low Quiescent Current
• 5 mm × 5 mm, 40-Pin, WQFN PowerPadTM
Package
• ASIC Needs Dual Power Rails
• High-Performance Processor Power
3 Description
The TPS53659 is a fully VR13 SVID compliant step-down controller with dual channels, built-in non- volatile memory (NVM), and PMBusTM interface, and is fully compatible with TI NexFETTM power stage. Advanced control features such as D-CAP+TM architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCORE slew rate and voltage positioning round out the Intel® features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
The TPS53659 device if offered in a thermally enhanced 40-pin WQFN packaged and is rated to operate from –40°C to 125°C.
Device Information
| PART NUMBER | PACKAGE | BODY SIZE | 
| TPS53659 | WQFN (40) | 5 mm × 5 mm | 
|   | 
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